1. Researching and Implementing of AI acceleration chip design.
2. Optimizing logic and chip for low power and high performance.
3. Verifying logic under simulation and estimating PPA before tape out.
4. Cooperating with other parts (application software).
1. BS/MS/PhD in Electronics Engineering or a related System LSI field.
2. At least 8 years of industry experience in design and verification of SoC/MCU/ASIC
3. Experiences in field of ASIC Design, Synthesis and Timing Closure
4. Solid design or verification experience of ASIC/SoC, such as that use standard IP components and interconnects, including microprocessor cores, hierarchical memory subsystems and SoC – AXI BUS, DMA, System MMU, interface Mixed IP such like USB, MIPI and LVDS
5. Mandatory Experience and Skills (one or more):
- HDL Design Language(Verilog, System Verilog), Synthesis Tools, DFT tool
- Architectural design experiences such like AMBA AXI, RISC CPU, Interconnect IP
- SoC IPs and memory architecture (USB/MIPI, MMU/Cache/Controller)
- Frontend design (Synthesis, STA, DFT, CDC) experience
6. Strong prior for low power design experiences, knowledge/experience in metric driven verification with SystemVerilog (creation of and usage of verification components and environments with OVM or UVM)
7.Strong prior experiences of ESL level modeling (with C/C++, or SystemC)
8.Must be able to communicate with team members in English.