AI 資深ASIC設計工程師
瀏覽人數: 227
投遞人數: 0
創惟科技(Genesys Logic)
全職
工作簡介
工作類型: 全職
經驗需求: 5 年以上
薪資範圍: 依能力經驗面議
刊登日期: 2019-02-22 11:05:01
有效期限: 2019-09-01
工作內容描述

【工作內容】
負責AI產品ASIC設計與驗證工作
1. Researching and Implementing of AI acceleration chip design.
2. Optimizing logic and chip for low power and high performance.
3. Verifying logic under simulation and estimating PPA before tape out.
4. Cooperating with other parts (application software).

【職務條件】
1. BS/MS/PhD in Electronics Engineering or a related System LSI field.
2. At least 8 years of industry experience in design and verification of SoC/MCU/ASIC
3. Experiences in field of ASIC Design, Synthesis and Timing Closure
4. Solid design or verification experience of ASIC/SoC, such as that use standard IP components and interconnects, including microprocessor cores, hierarchical memory subsystems and SoC – AXI BUS, DMA, System MMU, interface Mixed IP such like USB, MIPI and LVDS
5. Mandatory Experience and Skills (one or more):
- HDL Design Language(Verilog, System Verilog), Synthesis Tools, DFT tool
- Architectural design experiences such like AMBA AXI, RISC CPU, Interconnect IP
- SoC IPs and memory architecture (USB/MIPI, MMU/Cache/Controller)
- Frontend design (Synthesis, STA, DFT, CDC) experience
6. Strong prior for low power design experiences, knowledge/experience in metric driven verification with SystemVerilog (creation of and usage of verification components and environments with OVM or UVM)
7.Strong prior experiences of ESL level modeling (with C/C++, or SystemC)
8.Must be able to communicate with team members in English.

【創惟福利】
舒適安全及人性化的工作環境 
彈性上下班 
員工分紅,共享經營成果 
新人到職當年度即享特休假 
中秋、端午、勞動節、生日禮金 
每年員工健康檢查 
完善的團體保險 
每月慶生會活動 
完善教育訓練及補助 
高額人才推薦獎金 
一起微笑揮汗運動~登山、路跑等社團 
使你強健體魄~桌球、瑜珈等球類社團 
時下最紅的桌上益智遊戲~桌遊社團



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