1.Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development
2.Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model, and improve methodology
3.Develop testbench, test cases, reference model, coverage model and automation of regression suite
4.Run RTL and gate level functional verification, debug failures, manage bug tracking, and analyze and close coverage
|其他條件||1.Knowledge or working experience with Media or Video processing is a plus.
2.Experience with industry standard interfaces is a plus.
3.Experience with Emulator such as Palladium or ZeBu
4.Support mixed-signal co-simulation using Verilog models of analog IP.
5.Master's degree in Electrical Engineering or Computer Science with 5 years of relevant experience.
6.Advanced knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development
7.Expertise in HVL and HDL (SystemVerilog, Verilog)
8.Advanced knowledge of HVL methodology (UVM/OVM)
9.Solid verification skills in problem solving, constrained random testing, and debugging
10.Experience writing scripts in languages such as Perl or Python
11.Experience defining coverage space and writing coverage model
12.Experience with SystemVerilog Assertion (SVA)
13.Team player with excellent communication skills and the desire to take on diverse challenges